Method of forming silicon-on-insulator (soi) semiconductor substrate and soi semiconductor substrate formed thereby

ABSTRACT

A silicon-on-insulator (SOI) semiconductor substrate includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrates an SOI layer formed on the buried oxide layer, and a diffusion barrier layer interposed between the buried oxide layer and the SOI layer, wherein the diffusion barrier layer is an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.10/397,447, filed on Mar. 26, 2003, which claims priority to KoreanPatent Application No. 2002-28480, filed on May 22, 2002, thedisclosures of which are herein incorporated by reference in theirentirety.

FIELD OF THE INVENTION

The present invention relates to a method of forming a semiconductordevice and the semiconductor device formed thereby, more particularly, amethod of forming an SOI semiconductor substrate and the SOIsemiconductor substrate formed thereby.

BACKGROUND OF THE INVENTION

A typical transistor has a source/drain region, which is defined byforming an impurity diffusion layer at a semiconductor substrate. A PNjunction is formed between the source/drain region and the semiconductorsubstrate. Accordingly, the semiconductor substrate and the source/drainregion are electrically isolated from each other when a reverse bias isapplied therebetween.

With trends toward higher integration of semiconductor devices, a depthof the source/drain region is continually reduced. For this reason,current leakage, current leaked into the semiconductor substrate throughthe source/drain region, can become a serious problem. One proposedsolution to suppress the current leakage is by placing asilicon-on-insulator layer on the substrate (hereinafter referred to asan “SOI substrate”). The SOI substrate has a structure where a buriedoxide layer is disposed apart from a surface of the semiconductorsubstrate at a predetermined depth. The buried oxide layer may serve toprevent the leakage current through the source/drain region. However, inthe case that the impurities used to form the source/drain region areboron ions, the boron ions can be diffused into the buried oxide layer.

FIG. 1 is a cross-sectional view showing a transistor formed at an SOIsemiconductor substrate and FIG. 2 is a graph showing an impuritydensity, taken along a line I-I′ of FIG. 1. As illustrated in FIG. 2., ahorizontal axis represents a depth of a semiconductor substrate from asurface of an SOI layer and a vertical axis represents the impurityconcentration according to the depth of the semiconductor substrate.

Referring to FIGS. 1 and 2, buried oxide and SOI layers 2 and 3 aresequentially staked on an entire surface of a semiconductor substrate 1.A gate pattern 6 is disposed on an active region of the SOI layer 3 tocross over the active region. The gate pattern 6 consists of a gateinsulating layer 4 and a gate electrode 5, which are sequentiallystacked on the active region. An impurity diffusion layer 7 is disposedat both active regions of the gate pattern 6. The impurity diffusionlayer 7 corresponds to a source/drain region and is doped with boronions. Thus, a transistor having the foregoing structure is to be apositive-channel metal oxide semiconductor (“PMOS”) transistor.

A line ‘A’ of FIG. 2 represents the boron ions concentration accordingto the depth of the semiconductor substrate. As shown by line ‘A’, thesolubility and diffusion coefficient of the buried oxide layer 2 allowsboron ions to be diffused into the buried oxide layer 2. Further, theboron ions may be diffused into the semiconductor substrate 1 throughthe buried oxide layer 2. Therefore, resistance of the impuritydiffusion layer 7 is increased, thereby deteriorating characteristics ofthe transistor.

Also, in the case that the transistor is a negative-channel metal oxidesemiconductor (“NMOS”) transistor (not shown), the boron ions areimplanted into a channel region between the source and drain regions tocontrol a threshold voltage. In this case, the boron ions may bediffused into the buried oxide layer 2 or the semiconductor substrate 1.Thus, the concentration of the implanted boron ions is reduced to varythe threshold voltage of the NMOS transistor.

SUMMARY OF THE INVENTION

A feature of the present invention is to provide a method of forming anSOI semiconductor substrate that prevents impurities implanted into anSOI layer from being diffused into a buried oxide layer and asemiconductor substrate, and the SOI semiconductor substrate formedthereby,

In accordance with an aspect of the present invention, the invention isto provide a method of forming an SOI semiconductor substrate isprovided. The method according to an embodiment of the inventionincludes forming a porous silicon layer on a support substrate.Epitaxial and diffusion barrier layers are sequentially formed on theporous silicon layer. A buried oxide layer is formed on a handlesubstrate. The diffusion barrier layer is in contact with the buriedoxide layer to be bonded. The support substrate is etched until theporous silicon layer is exposed and the porous silicon layer is etcheduntil the epitaxial layer is exposed. The diffusion barrier layer isformed by an insulating layer having a lower impurity diffusioncoefficient as compared with the buried oxide layer. The epitaxial layeris an SOI layer. The diffusion barrier layer prevents impuritiesimplanted into the SOI layer from being diffused into the buried oxidelayer or the handle substrate.

More specifically, before forming the diffusion barrier layer, a bufferinsulating layer may be further formed on the epitaxial layer.

According to another embodiment of the present invention the methodincludes implanting hydrogen ions into a support substrate to form amicrobubble layer apart from a surface of the support substrate to apredetermined depth and to form an SOI layer on the microbubble layer. Adiffusion barrier layer is formed over the SOI layer. A buried oxidelayer is formed on a handle substrate. The diffusion barrier layer is incontact with the buried oxide layer to be bonded. The bonded support andhandle substrates are annealed to separate the support substrate fromthe SOI layer on the basis of the microbubble layer. Here, the diffusionbarrier layer is formed by an insulating layer having a lower impuritydiffusion coefficient as compared with the buried oxide layer.

Further, before forming the diffusion barrier layer, a buffer insulatinglayer may be further formed on the SOI layer.

According to still another embodiment of the present invention, themethod includes implanting oxygen ions into a semiconductor substrate toform an oxygen implantation layer apart from a surface of thesemiconductor substrate to a predetermined depth. Element ions areimplanted into the semiconductor substrate having the oxygenimplantation layer to form an element implantation layer. The elementimplantation layer is in contact with a top surface of the oxygenimplantation layer and is apart from the surface of the semiconductorsubstrate to a depth, which is tower than the predetermined depth. Thesemiconductor substrate having the element implantation layer isannealed to form buried oxide, diffusion barrier and SOI layers. At thistime, the oxygen implantation layer is formed by the buried oxide layerand the element implantation layer is formed by the diffusion barrierlayer. A portion of the semiconductor substrate on the diffusion barrierlayer is formed by the SOI layer.

In accordance with another aspect of the present invention, an SOIsemiconductor substrate includes semiconductor substrate and buriedoxide layer stacked on the semiconductor substrate. An SOI layer isdisposed on the buried oxide silicon layer and a diffusion barrier layeris intervened between the buried oxide silicon and SOI layers. Thediffusion barrier layer is formed by an insulating layer having a lowerimpurity diffusion coefficient as compared with the buried oxide layer.

More particularly, a buffer insulating layer may be further intervenedbetween the diffusion barrier and SOI layers

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a transistor formed at aconventional SOI semiconductor substrate.

FIG. 2 is a graph showing an impurity concentration, taken along a lineI-I′ of FIG. 1.

FIGS. 3 through 6 are cross-sectional views showing a method of formingthe SOI semiconductor substrate according to a preferred embodiment ofthe present invention.

FIGS. 7 through 11 are cross-sectional views showing the method offorming the SOI semiconductor substrate according to another embodimentof the present invention.

FIGS. 12 through 14 are cross-sectional views showing the method offorming the SOI semiconductor substrate according to still anotherembodiment of the present invention.

FIG. 15 illustrates an SOI semiconductor substrate according to anembodiment of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. The invention may, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. It will also be understood that when a layer is referred to asbeing “on” another layer or substrate, it can be directly on the otherlayer or substrate, or intervening layers may also be present. Likenumbers refer to like elements throughout.

FIGS. 3 through 6 are cross-sectional views showing a method of formingan SOI semiconductor substrate according to a preferred embodiment ofthe present invention.

Referring to FIGS. 3 and 4, a porous silicon layer 102 is formed on asupport semiconductor substrate 101 (hereinafter referred to as ‘supportsubstrate’) having single crystalline silicon.

An anodizing method may be used for forming the porous silicon layer102.

The anodizing method will be briefly explained as follows. First, asurface of the support substrate 101 is exposed to a reaction liquidincluding fluoric acid (HF). A negative voltage is applied to thesupport substrate 101 and a positive voltage is applied to the reactionliquid. Accordingly, the surface of the support substrate 101 ispartially oxidized and the oxidized portions are etched by the fluoricacid (HF). As a result, the porous silicon layer 102 with many pits isformed on the surface of the support substrate 101. The amount of timenecessary to form the porous silicon layer 102 or density of the poroussilicon layer 102 is related to the amount of an electric currentsupplied to the reaction liquid or a concentration of the reactionliquid.

Since the porous silicon layer 102 has a lower density than the supportsubstrate 101, it has an etch selectivity with respect to the supportsubstrate 101. On the other hand, the porous silicon layer 102 has thesame single crystalline structure as the support substrate 101.

An epitaxial layer 105 is formed on the porous silicon layer 102. Theepitaxial layer 105 is a silicon layer having a single crystallinestructure. This is because the porous silicon layer 102 has a singlecrystalline structure. Since the density of the epitaxial layer 105 ishigher than the porous silicon layer 102, the porous silicon layer 102has etch selectivity with respect to the epitaxial layer 105.

Preferably, a buffer insulating layer 110 is formed by a thermal oxidelayer on the epitaxial layer 105. In addition, the buffer insulatinglayer 110 may be formed by a CVD silicon oxide layer. A diffusionbarrier layer 115 is formed on the buffer insulating layer 110.

Meanwhile, a buried oxide layer 155 is formed on a handle semiconductorsubstrate 150 (hereinafter referred to as ‘handle substrate’). Theburied oxide layer 155 may be formed by thermal oxide or CVD siliconoxide layers.

The diffusion barrier layer 115 is formed by an insulating layer havinga lower impurity diffusion coefficient as compared with the buried oxidelayer 155. For example, it is preferable that the diffusion barrierlayer 115 is formed by the insulating layer having a lower boron ionsdiffusion coefficient. The diffusion barrier layer 115 may be composedof either one of a silicon nitride layer (SiN) and a silicon oxynitridelayer (SiON).

The buffer insulating layer 110 serves to alleviate a stress due to adifference between thermal expansion coefficients of the diffusionbarrier and epitaxial layers 115 and 110.

Referring to FIGS. 5 and 6, the diffusion barrier layer 115 disposed onthe support substrate 101 is in contact with the buried oxide layer 155disposed on the handle substrate 150 to be bonded. Here, the supportsubstrate 101 is disposed at an uppermost part of a bonded corporationand the handle substrate 150 may be disposed at a lowermost part of thebonded corporation.

Thereafter, the support substrate 101 is etched until the porous siliconlayer 102 is exposed because the porous silicon layer 102 has etchselectivity with respect to the support substrate 101. Here, a reactiveion etch method may be used for etching the support substrate 101.

The exposed porous silicon layer 102 is etched until the epitaxial layer105 is exposed. After exposing the epitaxial layer 105, a polishingprocess can be further performed to planarize the surface of theepitaxial layer 105.

Thus, the buried oxide, diffusion barrier and buffer insulating layers155, 115 and 110, which are stacked sequentially, are interposed betweenthe epitaxial layer 105 and the handle substrate 150. Here, theepitaxial layer 105 is used as a silicon-on-insulator (SOI) layer. As aresult, a SOI semiconductor substrate having the foregoing structure isformed. The diffusion barrier layer 115 may prevent impurities, such asthe boron ions, which are implanted into the SOI layer 105, from beingdiffused into the buried oxide layer 155 or the handle substrate 150.Therefore, degradation in characteristics of a transistor formed byimplanting impurities is prevented.

FIGS. 7 through 11 are cross-sectional views showing a method of formingan SOI semiconductor substrate according to another embodiment of thepresent invention. In this embodiment, elements having the same propertyor function as the elements of the foregoing embodiment refer to likenumbers and names. Referring to FIGS. 7, 8 and 9, hydrogen ions (H) areimplanted into the support substrate 101 to form a microbubble layer 117apart from the surface of the support substrate 101 to a predetermineddepth. At this time, a portion of the support substrate 101 on themicrobubble layer 117 becomes an SOI layer 120. The hydrogen ions (H)are implanted at a predetermined temperature. For example, the processmay be performed at a temperature of 500° C. The hydrogen ions have astrong tendency to secede from the support substrate 101, likewise, theimplanted hydrogen ions tend to secede from the support substrate 101due to the thermal energy obtained by the predetermined temperature. Asa result, the microbubble layer 117 is formed at a region where thehydrogen ions are implanted.

Preferably, the buffer insulating layer 110 is formed on the SOI layer120. The diffusion barrier layer 115 is formed on the buffer insulatinglayer 110.

It is preferable that the buffer insulating layer 110 is formed bythermal oxide or CVD silicon oxide layers. The buffer insulating layer110 serves to alleviate a stress between the diffusion barrier and SOIlayers 115 and 120.

The diffusion barrier layer 115 is formed by an insulating layer havinga lower impurity diffusion coefficient as compared with the buried oxidelayer 155. For example, it is preferable that diffusion barrier layer115 is formed by an insulating layer having a lower boron ions diffusioncoefficient. Preferably, the diffusion barrier layer 115 may be composedof either one of a silicon nitride layer (SiN) or a silicon oxynitridelayer (SiON).

The buried oxide layer 155 formed using the same method as the firstembodiment on the handle substrate 150 is in contact with the diffusionbarrier layer 115 to be bonded. Thus, the support and handle substrates101 and 150 are combined.

Referring to FIGS. 10 and 11, the combined support and handle substrates101 and 150 are annealed at different predetermined temperature.Accordingly, hydrogen gases in microbubble layer 117 have a thermalenergy to combine microbubbles. In this process, the support substrate101 is apart from the SOI layer 120 on the basis of the microbubblelayer 117. Thereafter, a polishing process is preferably performed toplanarize the surface of the SOI layer 120.

The diffusion barrier and buffer insulating layers 115 and 110, whichare sequentially stacked are interposed between the SOI and buried oxidelayers 120 and 155 by the foregoing method. The diffusion barrier layer115 may prevent the impurities such as the boron ions, which areimplanted into the SOI layer, from being diffused into the buried oxidelayer 155 or the handle substrate 150. Therefore, degradation incharacteristics of a transistor formed by implanting the impurities isprevented.

FIGS. 12 through 14 are cross-sectional views showing a method offorming an SOI semiconductor substrate according to still anotherembodiment of the present invention.

Referring to FIGS. 12, 13 and 14, oxygen ions (Ia) are implanted into asemiconductor substrate 201 to form an oxygen implantation layer 205apart from a surface of the semiconductor substrate 201 to apredetermined depth. Element ions (Ib) are implanted into thesemiconductor substrate 201 having the oxygen implantation layer 205 toform an element implantation layer 210. The element implantation layer210 is in contact with the oxygen implantation layer 205 and is apartfrom the surface of the semiconductor substrate 201 to a depth, which isless than the predetermined depth. Here, a portion of the semiconductorsubstrate 201 disposed on the element implantation layer 210 is formedto be an SOI layer 215.

The semiconductor substrate 201 having the element and oxygenimplantation layers 210 and 205 is annealed at a predeterminedtemperature to form buried oxide and diffusion barrier layers 205 a and210 a. At this time, the oxygen and element implantation layers 205 and210 are formed by the buried oxide and diffusion barrier layers 205 aand 210 a, respectively. In addition, lattices of the SOI layer 215,which are defected by implanting the ions (Ia and Ib), may be cured bythe annealing process.

The diffusion barrier layer 210 a is formed by an insulating layerhaving an impurity diffusion coefficient, which is lower than the buriedoxide layer 205 a. For example, the diffusion barrier layer 210 a ispreferably formed by the insulating layer having a lower boron ionsdiffusion coefficient. The diffusion barrier layer 210 a may be composedof either one of a silicon nitride layer (SiN) and a silicon oxynitridelayer (SiON).

In the case that the diffusion barrier layer 210 a is a silicon nitridelayer, nitrogen ions are preferably implanted into the elementimplantation layer 210. In the case that the diffusion barrier layer 210a is a silicon oxynitride layer, the nitrogen and oxygen ions arepreferably implanted into the element implantation layer 210.

The diffusion barrier layer 210 a may prevent impurities such as theboron ions, which are implanted into the SOI layer 215, from beingdiffused into the buried oxide layer 205 or the semiconductor substrate201. Therefore, degradation in characteristics of a transistor formed atthe SOI layer 215 is prevented.

FIG. 15 is an outline view showing an SOI semiconductor substrateaccording to an embodiment of the present invention.

According to an embodiment of the present invention, a semiconductordevice includes a handle substrate 150, a buried oxide, diffusionbarrier, buffer insulating and SOI layers 155, 115, 110 and 105 that aresequentially stacked.

Preferably, the buried oxide layer 155 is formed by a thermal oxidelayer. Additionally, the buried oxide layer 155 may be formed by a CVDsilicon oxide layer. The diffusion barrier layer 115 is formed of aninsulating layer having a lower impurity diffusion coefficient ascompared with the buried oxide layer 155. For example, the diffusionbarrier layer 115 is formed by the insulating layer having a tower boronions diffusion coefficient The diffusion barrier layer 115 may becomposed of either one of a silicon nitride layer (SiN) and a siliconoxynitride layer (SiON).

The diffusion barrier layer 115 prevents the impurities such as theboron ions, which are implanted into the SOI layer 105, from beingdiffused into the buried oxide layer 155 or the handle substrate 150.Therefore, degradation in characteristics of a transistor formed at theSOI layer 105 is prevented.

Preferably, the buffer insulating layer 110 is formed by the thermaloxide layer. Additionally., the buffer insulating layer 110 may beformed by the CVD silicon oxide layer. The buffer insulating layer 110suppresses a stress due to a difference between thermal expansioncoefficients of the SOI and diffusion barrier layers 105 and 115.

The SOI layer 105 may be formed by an epitaxial layer or a portion of asupport substrate.

According to an embodiment of the present invention as described above,the diffusion barrier layer is formed between the buried oxide and SOIlayers, which are sequentially stacked. The diffusion barrier layer mayprevent the impurities implanted into the SOI layer from being diffusedinto the buried oxide layer and the semiconductor substrate. Therefore,degradation in characteristics of the transistor formed on the SOI layeris prevented.

Although illustrative embodiments have been described herein withreference to the accompanying drawings, it is to be understood that thepresent disclosure is not limited to those precise embodiments, and thatvarious changes and modifications may be effected therein by one ofordinary skill in the pertinent art without departing from the scope orspirit of the present disclosure. All such changes and modifications areintended to be included within the scope of the present disclosure asset forth in the appended claims.

1. A silicon-on-insulator (SOI) semiconductor substrate comprising: asemiconductor substrate; a buried oxide layer formed on thesemiconductor substrate; an SOI layer formed on the buried oxide layer,and a diffusion barrier layer interposed between the buried oxide layerand the SOI layer, wherein the diffusion barrier layer is an insulatinglayer having a lower impurity diffusion coefficient as compared with theburied oxide layer.
 2. The SOI semiconductor substrate as claimed inclaim 1, wherein the buried oxide layer is silicon oxide formed bythermal oxidation or CVD.
 3. The SOI semiconductor substrate as claimedin claim 1, further comprising a buffer insulating layer interposedbetween the SOI layer and diffusion barrier layer.
 4. The SOIsemiconductor substrate as claimed in claim 3, wherein the bufferinsulating layer is silicon oxide formed by thermal oxidation or CVD. 5.The SOI semiconductor substrate as claimed in claim 1, wherein thediffusion barrier layer is the insulating layer having a lower borondiffusion coefficient as compared with the buried oxide layer.
 6. TheSOI semiconductor substrate as claimed in claim 1, wherein the diffusionbarrier layer comprises one of a silicon nitride layer or a siliconoxynitride layer.
 7. The SOI semiconductor substrate as claimed in claim1, wherein the SOI layer is an epitaxial layer composed of a singlecrystalline structure.